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System Documentation: RISC-V AI-SoC

Welcome to the official technical documentation for the CV32E40P-based AI-Accelerated SoC. This project is developed for the TÜBİTAK Chip Design Competition (Microcontroller Category), focusing on high-performance edge computing and modular hardware design.

Documentation Map

Identify your role to find the most relevant information:

I want to... Recommended Path
Run the project in 5 minutes πŸš€ Quick Start
Understand the Bus & Memory Topography πŸ—οΈ System Overview
Write Bare-Metal C Drivers πŸ’» Software Stack
Analyze the AI Math & Register Maps πŸ€– AI Accelerator
Debug RTL using Waveforms πŸ” Verification Guide

High-Level System Architecture

The following diagram illustrates the data flow between the RISC-V core, the interconnect, and the specialized peripherals.

graph TD
    subgraph "Core Domain"
        CPU[CV32E40P Core] -- "OBI (Open Bus Interface)" --> Bridge[OBI-to-AXI Bridge]
    end

    subgraph "Interconnect Fabric (AXI4)"
        Bridge -- "Master" --> Interconnect[AXI4 Crossbar/Interconnect]
    end

    subgraph "Slaves"
        Interconnect --> SRAM[Instruction SRAM - 8KB]
        Interconnect --> AI_ACC[AI Hardware Accelerator]
        Interconnect --> Periphs[Peripherals: UART, GPIO, Timer]
    end

Technical Specifications

  • ISA: RISC-V RV32IMFC (Compressed, Multiply, Atomic, Floating Point extensions).
  • Bus Protocol: AXI4-Full for high-speed memory/AI, AXI4-Lite for peripherals.
  • Clock Strategy: Single-clock domain for simulation (FPGA-ready synchronous design).
  • AI Unit: Fixed-point Matrix-Vector Multiplication (MVM) engine.

Getting Involved

If you are a team member joining the project:

  1. Environment: Set up your workspace using the Docker Guide.
  2. Coding Standards: Review the Coding Standards to maintain RTL and C consistency.
  3. Roadmap: Check the Github Page in the root directory for the current progress dashboard.